Accelerating Intelligent Automation
Intel® FPGA and SoC-based industrial automation solutions enable industrial system designers to innovate their system designs while reducing costs and time to market significantly. Our solutions can enable:
- Flexible multi-protocol industrial networking with Industrial Ethernet and IEEE802.1 TSN protocols
- Programmable logic controllers (PLC) with secure cloud connectivity
- Differentiated motor drives using Intel® SoC-based drive-on-a-chip and low-cost Intel® MAX® 10 FPGA
Intel TÜV-qualified safety package simplifies and speeds up the IEC61508 SIL 3 certification process. Intel provides complete FPGA Functional Safety Data Package (FSDP) which includes devices, IP, tools, tool flows, and reliability data.
Industrial Automation Transformation
The Industrial automation architecture is under transformation, using larger amounts of factory data from which AI systems can extract insights to continue increasing efficiencies. New sets of Industry standards, such as IEEE 802.1 TSN and OPC-UA, will allow the mix-and-match of industrial hardware and software solutions from different vendors.
Intel® FPGA based industrial ethernet and TSN solutions provide the connectivity for Industrial 4.0 factories to be smart, agile, and heading towards fully autonomous. FPGA based designs allow Industrial equipment manufactures to quickly add new features, such as functional safety and deep learning analytics, getting new products to market, which deliver best-in/class performance, seamless deterministic interoperability, and comply with safety and security requirements. For more information, please contact Intel sales.
Simplify Industrial Ethernet
- Manufacturers for factory automation, programmable logic controllers (PLCs), and motor control are challenged to implement a wide variety of industrial Ethernet protocols to support different end user requirements. Using Intel's highly integrated FPGAs and SoCs, easy-to-use development tools, and off-the-shelf intellectual property (IP), you can quickly develop products that are first to market, flexible, and cost effective.
|PROFIBUS||Softing||Cyclone® IV, Cyclone® V SoC, Arria® II|
|PROFINET RT||Softing||Cyclone® IV, Cyclone® V SoC|
|PROFINET IRT||Softing||Cyclone® IV, Cyclone® V SoC|
|EtherCAT||Softing||Cyclone® IV, Cyclone® V SoC|
|Ethernet POWERLINK||Softing||Cyclone® IV, Cyclone® V SoC|
|EtherNet/IP Soft DLR||Softing||Cyclone® IV, Cyclone® V SoC|
|Modbus TCP/IP||Softing||Cyclone® IV, Cyclone® V SoC|
Designing Industrial Ethernet with Softing and Intel
To make it easier to add Industrial Ethernet to your design, Intel and Softing Industrial Automation GmbH provide an out-of-the-box solution with no up-front license fees, no per-unit royalty reporting, and no protracted negotiations.
Simply download an entire Industrial Ethernet protocol including the software stack from Softing.
Three Steps to Design for Multiple Industrial Ethernet Protocols
- Download the protocol IP that you would like to use in production.
- Evaluate the protocol IP using the Intel® Quartus® Prime Design Software tool and the development kits.
- When you are ready to go into production, purchase a low-cost security CPLD for less than $3 each in 5,000+ unit volume through your local Intel sales representative.
You can use the same hardware for all the protocols listed below from PROFINET to Ethernet/IP to EtherCAT. You must purchase a security CPLD from Intel to enable any one protocol at a given time.
Download EtherCAT protocol now!
Download Ethernet/IP protocol now!
Download PROFINET RT/IRT protocol now!
Use the following application notes to help guide your PROFINET implementation:
- Application Note: PROFINET IRT: Getting Started with The Siemens CPU 315 PLC (PDF)
- Application Note: PROFINET Reference Design Bootstrap and Flash Access (PDF)
- Application Note: Adding New Design Components to the PROFINET IP (PDF)
- Altera Intel® FPGA Wiki: PROFINET Getting Started FAQ
Evaluating and Developing Solutions with Intel and Softing
Intel and Softing Industrial Automation GmbH provide an out-of-the-box solution with no up-front license fees, no per-unit royalty reporting, and no protracted negotiations. You have the flexibility to incorporate Industrial Ethernet using communications bridges, a communications peripheral, or by implementing a full system on an Intel® FPGA as shown in Figure.
Industrial Ethernet – Implementation Examples
1. Download the protocol(s) including the intellectual property and associated documentation package from the download tab at the bottom of the Softing's web page.
Note: Customer must become a member of the EtherCAT Technology Group (ETG) to use EtherCAT (membership is free). This provides a member identification number which must be input to the IP before compiling.
2. Select a platform for hardware evaluation, if needed.
3. Sign the Softing evaluation license agreement included in the documentation package for the protocol(s) of interest.
4. Evaluate and/or develop your system using the Intel® Quartus® Prime Design Software.
5. Take your design to production. The inclusion of a separate security CPLD addresses production licensing requirements. No additional licensing is required.
Take Your Design to Production
Production System Licensing
Intel and Softing enable you to quickly incorporate Industrial Ethernet into your product. Licensing is tracked using an external Security CPLD that unlocks the protocol IP loaded into the FPGA at boot time. For product development and protocol evaluation, the IP will function without the CPLD for several minutes and then time out. The Security CPLD is not required for pre-production activities.
The Security CPLD:
- Connects to the FPGA using a simple interface
- Tracks the number of licenses consumed - only pay for what you ship
- Works across multiple protocols. Load the protocol software of interest into the FPGA and go
- Can be used across multiple products. Mix and match protocols across your entire portfolio. Customize a product to meet customer requirements at compile time
- Available in four versions
Programmable Logic Controllers (PLC)
Intel Programmable Logic Controller (PLC) solutions for Internet of Things (IoT) and Industry 4.0 encompass single-chip high-end PLC implementations enabled with secure enterprise cloud connectivity and Human Machine Interface (HMI). Intel PLC-on-a-Chip solutions support full touch-screen HMI, Enterprise applications integration over OPC-UA, and Secure Sockets Layer (SSL) encryption in hardware, with up to 4X performance improvement over processor-based encryption, enabling significantly better bandwidth utilization for secure M2M and Enterprise communications.
Build PLCs Ready for Industry 4.0
Programmable logic controllers (PLCs) are at the heart of a factory control network. They are configured around an application processor that runs the factory control software along with any master communication protocol stack. Besides the processor, the PLC architecture requires support for multiple specialized peripherals, backplanes, and other custom interfaces, typically implemented using an FPGA.
Intel® SoCs provide a unique platform that allows you to implement both the application processor and FPGA in a single device.
Powering PLC-on-a-Chip with Intel® SoC
You can reduce system power, cost, and board space by integrating your processor, FPGA, and other required functionality, such as peripherals, into an Intel® SoC. To help you develop a complete PLC with integrated human machine interface (HMI) design more quickly onto a single chip, Intel teamed with:
- 3S-Smart Software Solutions GmbH, a leading PLC software developer
- EXOR International, a leader in HMI development
- Barco-Silex, a leader in security and encryption IP
The solution is a single chip implementation of a PLC with integrated HMI and secure enterprise connectivity over OPC-UA, including SSL encryption in FPGA fabric (up to 4X faster than processor-based implementations).
PLC on a Single Chip Implemented on an Intel® SoC
An Intel® SoC:
- Runs the PLC application software, Ethernet master protocol stack, and motion control software through the SoC’s dual-core ARM* Cortex*-A9 processor in Synchronous Multi Processing (SMP) or Asynchronous Multi Processing AMP mode
- Implements most peripherals, including USB, CAN, Ethernet, timers, and UARTs, required by the PLC system processor using the SoC’s hard processor system (HPS)
- Implements specialized peripherals such as multiport Ethernet switches and TCP/IP offload using the FPGA fabric
- Implements Human Machine Interface (HMI) in the FPGA fabric
- Implements IoT Cloud Server on SoC connecting to Enterprise over OPC-UA
- Implements Crypto Acceleration Engine for OpenSSL in FPGA fabric
Human Machine Interface (HMI) in PLC
Rich Human Machine Interface (HMI) including 3-D graphical user interfaces (GUI) with touchscreens is ubiquitous in today’s PLC designs enabling ease of operation and maintenance, operator training, information availability, and safety. Designing in a separate application processor for HMI operations is both expensive in terms of component cost and wasteful in terms of chip-to-chip data communication and resulting delay or latency between the HMI processor and the PLC processor. Using the hard processor system (HPS) of an SoC can mitigate both these problems but is wasteful in terms of processor cycles need to execute high-performance graphics.
HMI in FPGA Fabric Offloads Hard Processor System
Intel HMI solutions leverage the FPGA fabric, quite exclusive of the hard processor system. This approach not only enables integration of the HMI in the same SoC as the PLC but frees up the HPS from HMI related graphics computations by performing graphic acceleration and touch screen functions entirely in the FPGA fabric.
Drag-n-drop Symbol Library with CODESYS Integration
Intel HMI solution in the form of JMobile Studio Graphics Editor from Exor International for Cyclone® V SoC integrates directly with CODESYS PLC from 3S Software GmbH and provides an extensive symbol library to enable drag-n-drop HMI, building effective graphic interfaces for efficient representation of information making it easy to develop process control application using the integrated CODESYS PLC and HMI.
Secure Enterprise Communications over OPC-UA
OPC is the interoperability standard for the secure and reliable exchange of data in the industrial automation space and in other industries. It is platform independent and ensures the seamless flow of information among devices from multiple vendors. The OPC Foundation is responsible for the development and maintenance of this standard. The OPC Unified Architecture (UA), released in 2008, is a platform independent service-oriented architecture that integrates all the functionality of the individual OPC Classic specifications into one extensible framework.
Intel single-chip PLC design from Intel-partner Exor International integrates PLC, HMI, Gateway, and Cloud server in a single Cyclone® V SoC, with secure communications with Enterprise over OPC-UA. Security and encryption is enabled over OpenSSL with cryptographic acceleration IP from Intel-partner Barco-Silex.
FPGA Based Crypto Support for Secure IoT, M2M, and Enterprise Communications
Build Security into your PLC application with easy to integrate security and cryptography IP cores from Intel-partner Barco-Silex. FPGA fabric based implementation offers high performance and enhanced security, while scalable IP core footprint enables tailoring to suit customized needs.
BARCO Security SoC Solution for Cyclone® V SoC provides:
- API for custom OS or bare-metal programming
- Linux kernel drivers
- OpenSSL integration
- Hardware acceleration
- Symmetric: AES, SHA, DES
- Public key: RSA, ECC
- True Random Generator
- AXI* interface for easy integration
With up to 4X performance improvement over processor-based encryption, Intel® FPGA fabric-based security IP implementations enable significantly better bandwidth utilization for secure M2M and Enterprise communications.
Intel motor control solutions suite comprises reference designs, software libraries, intellectual property (IP) cores, and a portfolio of motor control hardware platforms and power boards supporting the development of complete single and multi-axis motor control systems in a single FPGA. From Drive-on-a-Chip reference designs to companion chip enhancement solutions Intel motor control solutions enable you to differentiate your drive offerings, using flexible SoC design methodologies. From C/C++ or Simulink models and using model-based and software-based tool flows from Intel and MathWorks, you can directly partition designs across embedded ARM* Cortex*-A9 processors and FPGA fabric in Intel® SoC devices.
Differentiate Your Drive
Motors and drives power countless industrial processes in production, assembly, packaging, robotics, computer numerical control (CNC), machine tools, pumps, and industrial fans. These motor-driven systems account for more than two-thirds of industrial energy consumption, making their efficient operations vital to factory profits.
Efficient Motor Control Designs with Intel® FPGAs and SoCs
Designing motor control and motion control systems with Intel® FPGAs and SoCs can result in significant reduction in overall cost of ownership through:
- System integration: Lower bill of materials (BOM), power consumption, and reliability challenges by integrating industrial networking, functional safety, encoder, and power stage interfaces and digital signal processing (DSP) control algorithms in a single device.
- Scalable performance: Use a single scalable platform across entire product lines. Achieve higher performance with faster and more advanced control loops.
- Functional safety: Reduce compliance time and effort. Intel is the first FPGA supplier to obtain qualification of our devices and tools under the Machinery Directive safety standard IEC 61508.
Drive-on-a-Chip with Intel® FPGAs
Unlike traditional motor control drive designs based on ASICs, ASSPs, microcontrollers, and DSP devices, a drive system based on a single Intel® FPGA platform, as shown in the figure above, provides a scalable platform that supports diverse drive needs.
Flexible Design Entry Methodologies - C/C++ and Simulink
Simplify your motor control design with flexible design entry methodologies from Intel. Intel motor control design flows are flexible to suit the particular needs of embedded software engineers, system/integration engineers, MATLAB*/Simulink* algorithm developers, and FPGA hardware engineers. Use software-based design flows to target the integrated ARM Cortex-A9 hard processor systems or Nios® II soft processors in Intel® FPGAs and SoCs.
Use Simulink and Embedded Coder from MathWorks to generate C/C++ code for Cyclone® V SoCs. When used in combination with Intel® SoC support from HDL Coder, this solution can be utilized in a hardware/software workflow spanning simulation, prototyping, verification, and implementation on Intel® SoCs. For more information, visit the MathWorks Intel® SoC FPGA Support page.
Intel Motor Control Development Framework
The Intel Motor Control Development Framework enables you to easily create integrated, high-performance drive-on-a-chip motor control designs for Intel® Cyclone® FPGAs and SoCs. The framework comprises reference designs, software libraries, intellectual property (IP) cores, and a portfolio of motor control hardware platforms supporting the development of motor control systems in a single FPGA.
The Motor Control Development Framework seamlessly integrates system-level design and software development tools for embedded Nios® II and ARM* processors, allowing you to extend and customize the motor control reference designs to meet your own application needs. The Intel® Cyclone® FPGAs, with high-performance fixed- and floating-point DSP functionality and Nios® II soft processor support, offer a scalable and flexible platform for integration of cost-effective single- and multiaxis drives on a single FPGA.
Power Conversion for Motor Control
Intel provides IP to implement flexible power conversion algorithms with an example design of a 2-phase bi-direction DC-DC converter including current and voltage control loops. Intel developed the FPGA IP using DSP Builder for Intel® FPGAs.
Intel Motor Control Reference Designs
Drive-on-a-Chip Motor Control Reference Design (Multiaxis)
Intel provides a suite of single-and multi-axis drive-on-a-chip reference designs that include a complete FOC IP subsystem integrated with key motor control and interface IP, and system software running on the integrated processor.
Drive-on-a-Chip Reference Design
The drive-on-a-chip reference design is a fully integrated single- and multiaxis motor control system implementation targeting Intel Cyclone® FPGAs and SoCs. The reference design, as shown in Figure 1, implements a software-configurable field-oriented-control (FOC) algorithm for concurrent control of up to four permanent magnet synchronous motors (PMSM) integrated with key motor control interface IP.
The motor control reference design includes the following features:
- Complete software system running on either the dual ARM Cortex-A9 hard processor system or a Nios® II processor, performing high-level control and configuration (in addition to closing of motor position and speed loops)
- Software-only and FPGA-accelerated FOC implementations interfacing position and speed loops in software with an ultra-low latency, high-performance current control loop in the FPGA as a DSP coprocessor
- Optimized and software-configurable FOC IP subsystem with support for both fixed- and floating-point precision implementations
- Integrates key motor control functions, such as space vector pulse-width modulation (PWM), Sigma-Delta ADC interface and filter logic, and position feedback encoder interfaces in the FPGA, all under control of software
- Motor Control Reference Design
Intel Motor Control Development Kits
|Type||Kit / Board Description||Vendor|
|FPGA Host Control Boards||Intel® MAX® 10 Development Kit||Intel|
|FPGA Host Control Boards||Intel Cyclone® V SoC Development Kit||Intel|
|Motor Control Power Board Options (Connect to FPGA Control Boards over HSMC)||Tandem Motion Power 48 V Board||Terasic|
|DC-DC Converter||Intel® MAX® 10 Development Kit||Intel|
Tandem Motion Power
The Cyclone® V SoC FPGA Development Kit, the SoCKit Development Kit from Terasic and the Intel® MAX® 10 FPGA Development Kit support the drive-on-a-chip motor control reference design. Designs running on the FPGA host boards connect to the dual axis Tandem Motion Power 48 V Board over a high-speed mezzanine card (HSMC) interface.
What’s new in Intel® FPGA Industrial Functional Safety Data Package (FSDP) version 5.0
The TÜV Rheinland certified functional safety data package V5.0 includes:
- TÜV Certificate
- FMEDA_MAX10 Tool
- AN-722: Industrial Safety FMEDA Tool
- fRSmartComp_nios2 LS IP
- Diagnostic IP V5.0
- Industrial Safety Manual for Intel® MAX® 10 FPGAs
- Industrial Safety Manual for Intel® Quartus® Prime Design Suite: 17.0.2
- AN-704: FPGA-based Safety Separation Design Flow for Rapid Certification
- AN-822: Intel® FPGA Configuration Device Migration Guideline
- Quartus® Prime 17.0 Handbook
- Quartus® Prime 17.0 IP User Guides
- Functional Safety Physics of Failure (PoF) Comparison Tool
- Motor Control Reference Design
- Reliability Report
The FSDP site can be accessed at: https://fpga-swdepot.intel.com/fsdp/
Revision history of the FSDP can be accessed at: https://fpga-swdepot.intel.com/full_fsdp/ce34ab1cb8368e3bac678398655435a9/
Reduce Time and Effort for Functional Safety Certification
Typical Dual-Channel SIL3 Industrial "Safe" System Implemented with Two FPGAs
TÜV-Qualified Safety Data Package Contents
- Guidelines on how to use the approved Intel® FPGA development methodology and tools to design IEC 61508 certifiable systems
- FMEDA tool allows calculation of failure rates and safe failure fraction (SFF) for Cyclone® V SoC designs
- Functional Safety Silicon Integration application note, showing how to qualify devices using the reliability report
- Functional Safety Tools and Tool Flow application note, showing how to use the Intel® Quartus® Prime Design Software and develop FPGA systems according to IEC 61508
- Diagnostic IP with IEC 61508 standard documentation and source code to monitor the integrity of the FPGA, memory, and clock signals
- Comprehensive guidelines on using the data to correctly calculate failure in time (FIT) rates of FPGA devices and systems required for safety certification
- Latest FPGA device reliability reports
- TÜV Rheinland qualification certificate
Qualification data at the FPGA device level means you can benefit from the flexibility of FPGAs without having to provide the required data and assessment for the IEC 61508 or equivalent standards. Normally, you would have to collect and document device and tool data for submission to the assessor. With Intel's Functional Safety Data Package, the device qualification process has been done for you. According to some of our customers, you can reduce system development time by up to two years from start to certification. TÜV is one assessor, and their standards are honored by the network of functional safety assessors.
The RTL coding guidelines can be used to improve code quality and reliability while helping to comply with requirements in the IEC 61508 standard.
Assessing your design for safety certification can be seamless. By following and adopting our FPGA-based certified design flow and methodology, as well as utilizing the included checklists, you can ensure high-quality project management and provision of the right project documentation.
To learn more about functional safety, please download the Developing Functional Safety Systems with TÜV-Qualified FPGAs (PDF) white paper and Reducing Steps to Achieve Safety Certification (PDF) white paper.
Safety Design Partitioning Toolflow
The Safety Separation Design Flow retains the FPGA benefits of quick upgrades/bug fixes while reducing the need for full design re-certification. The design flow guarantees that when changes are applied to non-safety regions, the safety regions are fully preserved, providing evidence that the placement and routing in the safety regions are identical to a previously certified design. To learn more about the Safety Separation Design Flow, please download the application note FPGA-based Safety Separation Design Flow for Rapid IEC 61508 Certification and contact your local Intel® FPGA representative for further information and access to the design example.
Nios II Lockstep
The Nios II Lockstep solution was developed by Intel to enable safety designers to utilize the flexibility of the already certified Nios® II processor, bringing their solutions to market, while meeting the stringent requirements of safety certification.
The lockstep solution provides high diagnostic coverage, self-checking, and advanced diagnostic features in full compliance with functional safety standards IEC 61508 and ISO 26262, while reducing the need for difficult to develop and performance sapping diagnostic software test libraries.
Applications for the Nios II lockstep solution include advanced motor control safety features such as SS1, SS2 in conjunction with safety encoder, and functional safety over industrial ethernet applications.
The Nios® II processor IP includes synthesizable register transfer level (RTL), safety manual, user guide and out of the box testbench. Contact your local Intel® representative for further information and access to the IP.
Nios II Qualification Kit
The Nios II QKit was developed by Validas AG to enable software designers to qualify the use of Nios II Toolchain in their safety application, fulfilling the requirements of IEC 61508 up to SIL 4 and ISO 26262 up to ASIL D.
Developing systems with the Nios II environment integrates parts of the Newlib library into the system. Therefore the Nios II QKit also supports library qualification of newlib by executing the contained library test cases on the target hardware.
The Intel Newlib library qualification kit contains:
- 2.4 million test cases in 4.600 files with 42.000 functions / equivalence classes
- Covers over 70 main functions of the newlib library
- Coverage reports showing the completeness of the tests for the Newlib library
- Qualification support tool to run tests on the target hardware and generate documents
- V&V Report and TÜV certificate
- Qualification user guide
- Document templates
Contact your local Intel representative for further information and access to the Nios II QKit.
SafeFlex, Safety Reference Board
The SafeFlex functional safety reference board and associated reference designs are designed by Intel and NewTec to reduce customer design effort for safety designs requiring IEC 61508 certification up to SIL3 and IEC 13849 PLe Cat 4. The board includes a reference design of a safety application together with documents describing the steps required to complete safety design from development of safety concept through to end product.
Contact NewTec for more information and to purchase the SafeFlex board.