Intel® 82566 Schematic Checklist (version 1.2) NOTE: Do not use with dual footprint designs. SECTION General CHECK ITEMS REMARKS Obtain the most recent documentation Documents are subject to frequent and specification updates. change. √ DONE Observe instructions for special pins Do not connect pull-up or pull-down needing pull-up or pull-down resistors. resistors to any pins marked No Connect, Test, or Reserved. Connect GLCI interface pins to GLCI corresponding pins on the ICH8 and Interface ICH9. Connect GLAN_RXP (pin J4) to PETp6/GLAN_TXp on ICH8 (pin B27) or on ICH9 (pin E28). Connect GLAN_RXN (pin H4) to PETn6/GLAN_TXn on ICH8 (pin B28) Correct polarity is mandatory, the GLCI or on ICH9 (pin E26). interface does not support polarity Connect GLAN_TXP (pin H2) to correction. PERp6/GLAN_RXp on ICH8 (pin C25) or on ICH9 (pin D30). Connect GLAN_TXN (pin J2) to PERn6/GLAN_RXn on ICH8 (pin C26) or on ICH9 (pin D29). Use only 0.1 µF Y5V capacitors on the GLCI interface. Recommend 0402 package size; however, 0603 is All GLCI interface AC coupling acceptable. capacitors are 0.1 µF, Y5V dielectric. There are a total of 4 coupling capacitors for the 82566. Connect LCI interface pins to LCI Interface corresponding pins on the ICH8 and ICH9. Connect JTXD[2:0] to LAN_TXD[2:0] The 82566 JTXD pins are inputs and the on the ICH. ICH LAN_TXD pins are outputs. Connect RTXD[2:0] to LAN_RXD[2:0] The 82566 JRXD pins are inputs and the on the ICH. ICH LAN_RXD pins are outputs. JKCLK connects to GLAN_CLK on the Reset/Clock The 33 Ω series resistor is required for all ICH through a 33 Ω, 5% series resistor. lengths of clock trace. Failure to use a Signals series terminating resistor results in signal integrity issues such as overshoot and ringing. Connect JRSTSYNC to Required for normal operation. LAN_RSTSYNC on the ICH. Parallel resonant crystals are required. Clock Source The load capacitance (Cload) should be Use 25 MHz 30 ppm accuracy@ 25 °C 20 pF. Specify Equivalent Series clock source. Avoid components that introduce jitter. Resistance (ESR) to be 50 Ω or less. Clock Source (continued) Capacitance affects accuracy of the frequency. Must be matched to crystal specifications stated in the datasheet, including estimated trace and pin capacitance. COMMENTS 1 Use capacitors with low ESR. Refer to the Intel 965 Express Chipset Family Connect two load capacitors to the Platform Design Guide for more details. crystal; one on XTAL1 and one on XTAL2. Use 27 pF 0402 capacitors. The two load capacitors, crystal component, the 82566, and the crystal circuit traces must all be located on the same side of the PCB (maximum of one via-to-ground load capacitor on each XTAL trace). Refer to Technical Advisory TA-181 for more details. The location of the resistor along the XTAL2 trace is flexible, as long as it is Connect a 30-ohm (5% tolerance) 0402 between the load capacitor and the series resistor on XTAL2 82566. LAN Controller Connect TEST_EN to GND with a 100 Required for normal operation. Ω resistor. Connect RBIAS_P to GND with a Read the full Project Name Fab Revision Date Designer Intel Contact Reviewer.